1. Field of the Invention
The present invention relates to a bus bridge for relaying data between devices that are connected to different buses.
2. Related Art
Conventionally, bus bridges are provided between buses in personal computers or computer systems equipped in information apparatuses, to meet the objectives of system expansion and smoothing out discrepancies in bus speed and bus width. (Construction of a Conventional Bus Bridge)
FIG. 1 is a block diagram showing a conventional bus bridge.
As illustrated, a bus bridge 10 is roughly made up of a primary bus interface 11, a secondary bus interface 12, a bus arbiter 13, a configuration register 14, and a data FIFO (First In, First Out) 15.
The primary bus interface 11 functions as an interface for a primary bus that can transfer data in burst mode, and also controls the data FIFO 15.
The secondary bus interface 12 functions as an interface for a secondary bus that can transfer data in burst mode, and also controls the data FIFO 15.
The primary bus and the secondary bus are, for example, 32-bit address/data multiplexer buses of PCI (Peripheral Component Interconnect).
The bus arbiter 13 arbitrates between the bus bridge 10 and a master of the secondary bus, for ownership of the secondary bus.
Here, a master is also called a “bus master”. A bus master is a device that drives address lines of a bus to indicate a device that is the data transfer destination, and sends a bus command to the indicated device. In this specification, a device that alone acts as bus master in a data transfer is referred to as an “initiator”.
The configuration register 14 holds configuration information that determines basic operations of the bus bridge 10. The configuration information is based on a format described in the PCI-to-PCI Bridge Architecture Specification and the like.
The data FIFO 15 includes a downstream data FIFO (hereafter a “DS data FIFO”) 16 and an upstream data FIFO (hereafter a “US data FIFO”) 17.
The DS data FIFO 16 holds an address, a bus command, a byte enable, data, and the like which relate to a bus cycle that is initiated by an initiator of the primary bus to read from or write to a target of the secondary bus. When the bus bridge 10, as an initiator of the secondary bus, initiates a bus cycle to read from or write to the target, this information held in the DS data FIFO 16 is driven onto the secondary bus.
Here, a target is a device that receives an address and a bus command, decodes the received address and bus command, and sends back a response.
The US data FIFO 17 holds an address, a bus command, a byte enable, data, and the like which relate to a bus cycle that is initiated by an initiator of the secondary bus to read from or write to a target of the primary bus. When the bus bridge 10, as an initiator of the primary bus, initiates a bus cycle to read from or write to the target, this information held in the US data FIFO 17 is driven onto the primary bus.
In a read transaction, the bus bridge 10 reads data from a target until a predetermined size of data (e.g. 8 entries) is stored in the data FIFO 15. Note here that addresses, bus commands, and byte enables are not counted as entries.
In this specification, one entry is 4 bytes (32 bits), so that 8 entries are 32 bytes.
Here, the bus bridge 10 may read data which is not required by an initiator.
For instance, when the initiator needs 2 entries of data, the bus bridge 10 reads 8 entries of data from the target, so that the remaining 6 entries will end up being unnecessary.
Reading such unnecessary data from the target causes a problem of prolonging the time during which the bus bridge 10 occupies the bus to which the target is connected.